In general, in a semiconductor device, serializing signals means serially outputting a plurality of signals, which are inputted in parallel through a plurality of input lines, through one output line. A multiplexer has been used to serialize the signals.
However, in order for the multiplexer to serialize the signals without collision, a signal for determining when each of the signals input to the multiplexer in parallel should be outputted through one output line is required. If the semiconductor device operates in a synchronous-type mode, the signal for determining the output timing of the inputted signals should be enabled and synchronized with a system clock inputted from an external source.
Therefore, in the prior art, multi-phase clock signals are used to control an operation of the multiplexer, where the multi-phase clock signals are generated by dividing the system clock to have a predetermined phase difference.
FIG. 1 illustrates a circuit diagram of a multiplexer for serializing input/output signals in a conventional semiconductor device.
Referring to FIG. 1, the multiplexer includes a plurality of synchronization blocks 100A, 100B, 100C, and 100D and a serialization block 120.
The plurality of synchronization blocks 100A, 100B, 100C and 100D receive a plurality of input/output signals D_IN<0>, D_INB<0>, D_IN<1>, D_INB<1>, D_IN<2>, D_INB<2>, D_IN<3> and D_INB<3> in parallel, which swing in a complementary metal oxide semiconductor (CMOS) region or a current mode logic (CML) region, and sequentially synchronizes the received input/output signals with multi-phase clock signals CLK<0>, CLK<1>, CLK<2> and CLK<3>. Therefore, a plurality of output signals D_OUT<0>, D_OUTB<0>, D_OUT<1>, D_OUTB<1>, D_OUT<2>, D_OUTB<2>, D_OUT<3> and D_OUTB<3>, which swing in the CML region, are outputted.
The serialization block 120 serializes the plurality of output signals D_OUT<0>, D_OUTB<0>, D_OUT<1>, D_OUTB<1>, D_OUT<2>, D_OUTB<2>, D_OUT<3> and D_OUTB<3>, which are outputted from the plurality of synchronization blocks 100A, 100B, 100C and 100D, respectively. The serialized signals MUXOUTB and MUXOUT are outputted.
Herein, it is noted that each of the synchronization blocks 100A, 100B, 100C, and 100D included in the conventional multiplexer is designed according to a differential scheme of simultaneously transmitting a pair of signals divided to have contrary phases. Because the plurality of synchronization blocks 100A, 100B, 100C, and 100D have the same configuration, except for inputted signals, the synchronization block 100A is illustrated in detail and will be described below for purposes of convenience. It should be understood that the description of the synchronization block 100A is applicable to the remaining blocks 100B, 100C, and 100D.
In particular, the differential input/output signals D_IN<0> and D_INB<0> having contrary phases are inputted to the synchronization block 100A. Accordingly, the synchronization block 100A synchronizes the differential input/output signals D_IN<0> and D_INB<0> with the multi-phase clock signals CLK<0> and CLK<1>, and outputs the differential output signals D_OUT<0> and D_OUTB<0>, where the output signals have contrary phases.
Likewise, it is noted that the serialization block 120 included in the conventional multiplexer is also designed according to the differential scheme to simultaneously transmit two signals having contrary phases.
In particular, the serialization block 120 receives the plurality of signals grouped into a differential signals of pairs, i.e., D_OUT<0> and D_OUTB<0>, D_OUT<1> and D_OUTB<1>, D_OUT<2> and D_OUTB<2>; and D_OUT<3> and D_OUTB<3>, from the plurality of synchronization blocks 100A, 100B, 100C, and 100D. The serialization block 120 divides and serializes the received signals into positive signals D_OUT<0>, D_OUT<1>, D_OUT<2>, and D_OUT<3>; and negative signals D_OUTB<0>, D_OUTB<1>, D_OUTB<2>, and D_OUTB<3>, to output two signals MUXOUT and MUXOUTB that have contrary phases.
As described above, since the conventional multiplexer is designed with the differential scheme of dividing its input/output signals into differential signals having contrary phases and simultaneously outputting the differential signals, the conventional multiplexer can perform the stable multiplexing although the input/output signals swinging in the CML region have a high frequency greater than a giga-hertz or dozens of giga-hertz.
However, the signals of the conventional multiplexer are determined not by their potential levels but their logic levels. That is, on the basis of a logic determination level, the input/output signals are recognized as a logic high level when they swing with a potential level higher than the logic determination level and as a logic low level when they swing with a potential level lower than the logic determination level. When controlling the input/output signals to swing in the CML region like in the conventional multiplexer, several problems may occur.
First of all, controlling the input/output signals to swing in the CMOS region will be described. Since controlling the input/output signals to swing in the CMOS region means controlling the input/output signals to full-swing between a supply voltage (VDD) level and a ground voltage (VSS) level, in a typical semiconductor device using a supply voltage (VSS) and a ground voltage (VSS) as voltage sources, the logic determination level is naturally set to a middle level between the VDD level and the VSS level and thus a region recognized as the logic high, i.e., a range of potential levels higher than the logic determination level, and a region recognized as the logic low, i.e., a range of potential levels lower than the logic determination level naturally have the same size.
However, like in the multiplexer, since controlling the signal to swing in the CML region means controlling the signal to swing between the VDD level and a potential level higher than the VSS level or between a potential level lower than the VDD level and the VSS level or between a potential level lower than the VDD level and a potential level higher than the VSS level, in the typical semiconductor device using the VDD and the VSS as voltage sources, the control for properly adjusting a reference level of the CML region is additionally required to make the region recognized as the logic high, i.e., the range of potential levels higher than the logic determination level, and the region recognized as the logic low, i.e., the range of potential levels lower than the logic determination level have the same size.
Further, the conventional multiplexer uses the differential scheme of dividing its signals into differential signals that have contrary phases and simultaneously transmitting the differential signals in order to input/output signals swinging in the CML region. At this time, in case of the differential scheme, it has an advantage of securing stability against noise that may occur during transmission of the signals swinging in the CML region. On the other hand, it has a disadvantage of requiring separate signal transmission lines for transmitting the differential signals having contrary phases and circuits for inputting/outputting the differential signals.
Specially, since the conventional multiplexer described in FIG. 1 is a circuit for directly processing signals that are inputted/outputted, the conventional multiplexer is used in a number of locations where signals are inputted/outputted in the semiconductor device. Therefore, the size of the semiconductor device including the conventional multiplexer is substantially changed according to whether the multiplexer is designed using the differential scheme of simultaneously transmitting two signals or a single-ended scheme of transmitting one signal.
Herein, if the size of the semiconductor device becomes greater, the cost of production is also increased. Therefore, in case of employing the conventional multiplexer using the differential scheme as described in FIG. 1, the size of the semiconductor device becomes much greater compared to the case of designing the multiplexer using the single-ended scheme, so that the cost of production is substantially increased.